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LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
The MPC940L is a 1:18 low voltage clock distribution chip with 2.5 V or 3.3 V LVCMOS output capabilities. The device features the capability to select either a differential LVPECL or an LVCMOS compatible input. The 18 outputs are 2.5 V or 3.3 V LVCMOS compatible and feature the drive strength to drive 50 series or parallel terminated transmission lines. With output-to-output skews of 150 ps, the MPC940L is ideal as a clock distribution chip for the most demanding of synchronous systems. The 2.5 V outputs also make the device ideal for supplying clocks for a high performance microprocessor based design. For a similar device at a lower price/performance point, the reader is referred to the MPC9109. * * * * * * * LVPECL or LVCMOS Clock Input 2.5 V LVCMOS Outputs for Pentium II Microprocessor Support 150 ps Maximum Output-to-Output Skew Maximum Output Frequency of 250 MHz 32-Lead LQFP Packaging 32-Lead Pb-Free Package Available Dual or Single Supply Device: * Dual VCC Supply Voltage, 3.3 V Core and 2.5 V Output * Single 3.3 V VCC Supply Voltage for 3.3 V Outputs * Single 2.5 V VCC Supply Voltage for 2.5 V I/O
MPC940L
MPC940L
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-04
With a low output impedance (20 ), in both the HIGH and LOW logic states, the output buffers of the MPC940L are ideal for driving series terminated transmission lines. With a 20 output impedance the 940L has the capability of driving two series terminated lines from each output. This gives the device an effective fanout of 1:36. If a lower output impedance is desired please see the MPC942 data sheet.
AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-04
The differential LVPECL inputs of the MPC940L allow the device to interface directly with a LVPECL fanout buffer like the MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH on the LVCMOS_CLK_SEL pin will select the LVCMOS level clock input. All inputs of the MPC940L have internal pullup/pulldown resistors so they can be left open if unused. The MPC940L is a single or dual supply device. The device power supply offers a high degree of flexibility. The device can operate with a 3.3 V core and 3.3 V output, a 3.3 V core and 2.5 V outputs as well as a 2.5 V core and 2.5 V outputs. The 32-lead LQFP package was chosen to optimize performance, board space and cost of the device. The 32-lead LQFP has a 7x7 mm body size with a conservative 0.8 mm pin spacing.
Pentium II is a trademark of Intel Corporation.
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MPC940L LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
PECL_CLK PECL_CLK LVCMOS_CLK LVCMOS_CLK_SEL (Internal Pulldown)
LOGIC DIAGRAM
0 1 16
Q0 Q1-Q16 Q17
Pinout: 32-Lead LQFP (Top View)
GND 17 16 15 14 VCCO Q12 Q13 Q14 GNDO Q15 Q16 Q17 VCCI Q10 19 Q11 18 Q6 Q7 Q8 Q9 20
24 GNDO Q5 Q4 Q3 VCCO Q2 Q1 Q0 25 26 27 28 29 30 31 32 1
23
22
21
FUNCTION TABLE
LVCMOS_CLK_SEL 0 1 Input PECL_CLK LVCMOS_CLK
MPC940L
13 12 11 10 9
POWER SUPPLY VOLTAGES
Supply Pin VCCI VCCO Voltage Level 2.5 V or 3.3 V 5% 2.5 V or 3.3 V 5%
2
3
4
5
6
7
8
LVCMOS_CLK_SEL
GNDI
GNDO
LVCMOS_CLK
PECL_CLK
PECL_CLK
VCCI
Table 1. Pin Configurations
Pin PECL_CLK PECL_CLK LVCMOS_CLK LVCMOS_CLK_SEL Q0-Q17 VCCO VCCI GNDO GNDI I/O Input Input Input Output Type LVPECL LVCMOS LVCMOS LVCMOS Supply Supply Supply Supply Reference Clock Input Alternative Reference Clock Input Selects Clock Source Clock Outputs Output Positive Power Supply Core Positive Power Supply Output Negative Power Supply Core Negative Power Supply Function
IDTTM / ICSTM 1:18 CLOCK DISTRIBUTION CHIP
VCCO
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Table 2. Absolute Maximum Ratings(1)
Symbol VCC VI IIN TStor Supply Voltage Input Voltage Input Current Storage Temperature Range -40 Parameter Min -0.3 -0.3 Max 3.6 VDD + 0.3 20 125 Unit V V mA C
1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied.
Table 3. DC Characteristics (TA = 0 to 70C, VCCI = 3.3 V 5%; VCCO = 3.3 V 5%)
Symbol VIH VIL VPP VCMR VOH VOL IIN CIN Cpd ZOUT ICC Characteristic Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode Range Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current 18 4.0 10 23 0.5 28 1.0 CMOS_CLK CMOS_CLK PECL_CLK PECL_CLK 500 VCCI - 1.4 2.4 0.5 200 Min 2.4 Typ Max VCCI 0.8 1000 VCCI - 0.6 Unit V V mV V V V A pF pF mA per output IOH = -20 mA IOL = 20 mA Condition
Table 4. AC Characteristics (TA = 0 to 70C, VCCI = 3.3 V 5%; VCCO = 3.3 V 5%)
Symbol Fmax tPLH tPLH tsk(o) tsk(pp) tsk(pp) tsk(pp) DC tr, tf Characteristic Maximum Input Frequency Propagation Delay Propagation Delay PECL_CLK 150 MHz CMOS_CLK 150 MHz PECL_CLK > 150 MHz CMOS_CLK > 150 MHz PECL_CLK CMOS_CLK 2.0 1.8 2.0 1.8 2.7 2.5 2.9 2.4 Min Typ Max 250 3.4 3.0 3.7 3.2 150 150 1.4 1.2 1.7 1.4 850 750 45 40 0.3 50 50 55 60 1.1 Unit MHz ns ns ps ns ns ps % % ns Note (1) Note (1) Note (2) Input DC = 50% Input DC = 50% 0.5 - 2.4 V Condition
Output-to-Output Skew Part-to-Part Skew Part-to-Part Skew Part-to-Part Skew Output Duty Cycle Output Rise/Fall Time
PECL_CLK 150 MHz CMOS_CLK 150 MHz PECL_CLK > 150 MHz CMOS_CLK > 150 MHz PECL_CLK CMOS_CLK fCLK < 134 MHz fCLK 250 MHz
1. Across temperature and voltage ranges. Includes output skew. 2. For specific temperature and voltage. Includes output skew.
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Table 5. DC Characteristics (TA = 0 to 70C, VCCI = 3.3 V 5%; VCCO = 2.5 V 5%)
Symbol VIH VIL VPP VCMR VOH VOL IIN CIN Cpd ZOUT ICC Characteristic Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode Range Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current 4.0 10 23 0.5 1.0 CMOS_CLK CMOS_CLK PECL_CLK PECL_CLK 500 VCCI - 1.4 1.8 0.5 200 Min 2.4 Typ Max VCCI 0.8 1000 VCCI - 0.6 Unit V V mV V V V A pF pF mA per output IOH = -12 mA IOL = 12 mA Condition
Table 6. AC Characteristics (TA = 0 to 70C, VCCI = 3.3 V 5%; VCCO = 2.5 V 5%)
Symbol Fmax tPLH tPLH tsk(o) tsk(pp) tsk(pp) tsk(pp) DC tr, tf Characteristic Maximum Input Frequency Propagation Delay Propagation Delay PECL_CLK 150 MHz CMOS_CLK 150 MHz PECL_CLK > 150 MHz CMOS_CLK > 150 MHz PECL_CLK CMOS_CLK 2.0 1.7 2.0 1.8 2.8 2.5 2.9 2.5 Min Typ Max 250 3.5 3.0 3.8 3.3 150 150 1.5 1.3 1.8 1.5 850 750 45 40 0.3 50 50 55 60 1.2 Unit MHz ns ns ps ns ns ps % % ns Note (1) Note (1) Note (2) Input DC = 50% Input DC = 50% 0.5 - 1.8 V Condition
Output-to-Output Skew Part-to-Part Skew Part-to-Part Skew Part-to-Part Skew Output Duty Cycle Output Rise/Fall Time
PECL_CLK 150 MHz CMOS_CLK 150 MHz PECL_CLK > 150 MHz CMOS_CLK > 150 MHz PECL_CLK CMOS_CLK fCLK < 134 MHz fCLK 250 MHz
1. Across temperature and voltage ranges. Includes output skew. 2. For specific temperature and voltage. Includes output skew.
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Table 7. DC Characteristics (TA = 0 to 70C, VCCI = 2.5 V 5%; VCCO = 2.5 V 5%)
Symbol VIH VIL VPP VCMR VOH VOL IIN CIN Cpd ZOUT ICC Characteristic Input HIGH Voltage Input LOW Voltage Peak-to-Peak Input Voltage Common Mode Range Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current 18 4.0 10 23 0.5 28 1.0 CMOS_CLK CMOS_CLK PECL_CLK PECL_CLK 500 VCCI - 1.0 1.8 0.5 200 Min 2.0 Typ Max VCCI 0.8 1000 VCCI - 0.6 Unit V V mV V V V A pF pF mA per output IOH = -12 mA IOL = 12 mA Condition
Table 8. AC Characteristics (TA = 0 to 70C, VCCI = 2.5 V 5%; VCCO = 2.5 V 5%)
Symbol Fmax tPLH tPLH tsk(o) tsk(pp) tsk(pp) tsk(pp) DC tr, tf Characteristic Maximum Input Frequency Propagation Delay Propagation Delay PECL_CLK 150 MHz CMOS_CLK 150 MHz PECL_CLK > 150 MHz CMOS_CLK > 150 MHz PECL_CLK CMOS_CLK 2.6 2.3 2.8 2.3 4.0 3.1 3.8 3.1 Min Typ Max 200 5.2 4.0 5.0 4.0 200 200 2.6 1.7 2.2 1.7 1.2 1.0 45 40 0.3 50 50 55 60 1.2 Unit MHz ns ns ps ns ns ns % % ns Note (1) Note (1) Note (2) Input DC = 50% Input DC = 50% 0.5 - 1.8 V Condition
Output-to-Output Skew Part-to-Part Skew Part-to-Part Skew Part-to-Part Skew Output Duty Cycle Output Rise/Fall Time
PECL_CLK 150 MHz CMOS_CLK 150 MHz PECL_CLK > 150 MHz CMOS_CLK > 150 MHz PECL_CLK CMOS_CLK fCLK < 134 MHz fCLK 200 MHz
1. Across temperature and voltage ranges. Includes output skew. 2. For specific temperature and voltage. Includes output skew.
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MPC940L DUT Pulse Generator Z = 50 ZO = 50 ZO = 50
RT = 50 VTT
RT = 50 VTT
Figure 1. LVCMOS_CLK MPC940L AC Test Reference for VCC = 3.3 V and VCC = 2.5 V
Differential Pulse Generator Z = 50
ZO = 50
MPC940L DUT ZO = 50
RT = 50 VTT
RT = 50 VTT
Figure 2. PECL_CLK MPC940L AC Test Reference for VCC = 3.3 V and VCC = 2.5 V
VCC VPP VCMR VCC VCC /2 GND tPD LVCMOS_CLK VCC / 2 GND Q tPD VCC VCC / 2 GND
PCLK_CLK PCLK_CLK
Q
Figure 3. Propagation Delay (tPD) Test Reference
Figure 4. LVCMOS Propagation Delay (tPD) Test Reference
VCC VCC / 2 tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage. tSK(O) GND
VCC VCC / 2 GND VOH VCC / 2 GND
The pin-to-pin skew is defined as the worst case difference in propagation delay between any two similar delay paths within a single device.
Figure 5. Output Duty Cycle (DC)
Figure 6. Output-to-Output Skew TSK(O)
VCC = 3.3 V VCC = 2.5 V 2.4 0.55 tF tR 1.8 V 0.6 V tF tR
VCC = 3.3 V VCC = 2.5 V 2.0 0.8 1.7 V 0.7 V
Figure 7. Output Transition Time Test Reference
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Figure 8. Input Transition Time Test Reference
MPC940L REV 7 JUNE 5, 2007
MPC940L LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
PACKAGE DIMENSIONS
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CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE
IDTTM / ICSTM 1:18 CLOCK DISTRIBUTION CHIP 7 MPC940L REV 7 JUNE 5, 2007
MPC940L LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
PACKAGE DIMENSIONS
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CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE
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PACKAGE DIMENSIONS
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CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE
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Ordering Information
Table 9. Ordering Information
Part/Order Number MPC940LFA MPC940LFAR2 MPC940LAC MPC940LACR2 Marking MPC940L MPC940L MPC940LAC MPC940LAC Package 32 Lead LQFP 32 Lead LQFP Lead-Free, 32 Lead LQFP Lead-Free, 32 Lead LQFP Shipping Packaging Tray 2500 Tape & Reel Tray 2500 Tape & Reel Termperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
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(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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